FPGA/ASIC Design Engineer (Secret Clearance) - Camden, NJ - 2380 with Security Clearance

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Job description

We've determined which skillsets are most beneficial for this role. These skills are listed first below as the Must Haves and Nice to Haves our hiring team highly prefers. Below that you'll find the standard job description for this opportunity. Must Haves:
Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
At least 3 years of experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs
Proficiency in VHDL and FPGA design/debug - Xilinx FPGA / Vivado
Excellent Analytical/Debug skills
Good verbal, written, and presentation skills
Nice to Haves:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
Job Description:
The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.
Essential Functions:
Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols- NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
Company has deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS). Please see our website for more job openings:

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