Please scroll down, To apply

Senior Physical Design Engineer (remote)

hiring now
New job

Chelsea Search Group

2024-10-05 19:45:33

Job location Austin, Texas, United States

Job type: all

Job industry: Engineering

Job description

Senior Physical Design Engineer (remote)
Start Date: by November 4
Work Status: US Citizen only
Hourly Rate: $80-$90 on 1099 or C2C
100% remote / work from any US location
6-12 months contract with possible extensions

The ideal candidates should be highly proficient in using all the Synopsys EDA tools/flows with little to no ramp-up time needed to make an immediate impact. You will be responsible for doing all aspects of SOC Physical Design implementation.

Required Qualifications:
Experience: 10+ years
Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)
Synopsys DC, DCG, DC TOPO
Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by customers Physical Design Implementation team members
- Familiar with Synopsys Lynx a plus
RTL Hand-over experience a plus for RTL to GDS
Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning
Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)
Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off
- Ability to define sign-off requirements/margins based on Foundry technology requirements a plus
DFT experience with compression, scan, TDF, and MEMBIST a plus
Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows
Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF
Synopsys ICV for PV (Physical Verification DRC/ERC/LVS/PERC)
Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR )
Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus
Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus
Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out



Javier Leon

cell

removed)

Inform a friend!

<!– job description page –>
Top